A programmable logic device, such as a field programmable gate array (FPGA), is designed to be user-programmable so that users can implement logic designs of their choices. In a typical FPGA, an array of configurable logic blocks (CLBs) are coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into configuration memory cells of the FPGA. As circuit designs implemented in an FPGA are becoming more complex, the number of CLBs, IOBs, and other resources such as multipliers and block RAMs has increased, as well as the generalized routing resources to make the connections between the various blocks. The length of a conductors providing routing resources are often defined by the number of conductor segments coupled between a pair of programmable interconnect points (PIPs). Relatively short conductors (e.g. “double lines” comprising two segments between PIPs) could be included in a first pair of metal layers. Similarly, “hex lines” comprising six segments coupled between PIPs could be formed on another pair of metal layers, while relatively long conductors extending between the edges of the integrated circuit could be formed on another pair of metal layers. As a result, the size of FPGA die and the resources fabricated on the die has grown. Because the number of defects is proportional to the area of a die, the probability of having a defect in a die has also increased.
The circuits implemented by different customers using FPGAs are usually unique. Further, a circuit design may undergo modifications during product development phase. Thus, multiple versions of a circuit may be implemented on an FPGA. Because FPGAs are not design specific and can be used with any design, the quality and reliability of FPGAs is very significant. If an FPGA contains a single defect (e.g., one of its configuration memory cells is defective), it may render an end product unusable because a customer design may need to use that defective resource. In order to avoid problems with customers, an FPGA manufacturer needs to discard an FPGA even if it contains only one defect. The problem of low yield has significant economic impact on FPGA manufacturers.
While a gross defect causes failure of an entire FPGA, a localized defect may cause the failure of a small amount of circuitry in the FPGA. It has been found that a majority of large FPGA dies are discarded because of localized defects. Methods have been found to use some of these defective dies, significantly reducing the product cost of the FPGA manufacturer. In particular, it may be determined that a defect in a given FPGA die will not affect the customer's design, making that given defective die suitable for the customer. For example, a user may program a predetermined circuit design in the defective die. If the design works, the die would be acceptable to the customer. As a result, customers can take advantage of lower priced FPGAs for specific design patterns.
However, it is often the case that a given defective FPGA die may not function for a predetermined circuit design as configured, but may function if reconfigured so that different elements of the defective die are used to implement the correct circuit design. One element of an FPGA which may be defective is a lookup table. The majority of lookup tables of an FPGA are often used when an FPGA is configured with a design. However, testing lookup tables in an FPGA can require significant routing overhead (i.e. the portion of the FPGA that is not part of the predetermined circuit design). As shown for example in FIG. 1, a configurable logic block 102 having a plurality of lookup tables 104 are coupled to an input/output block 106 having a plurality of inputs 108. Four address bits are shown for addressing the lookup tables by way of routing resources 110. The typical technique to test the lookup table of a defective device is to stimulate all used input combinations of the lookup table, for all of the lookup tables to be programmed to implement the design. For example, when all four inputs of the lookup table are used, the lookup table has to be tested using 16 combinations of input values. Conventional techniques provide the stimulus for the 4 inputs through the IOB pads. For each input, an IOB pad is configured and connected to drive that input. Therefore, a total of four IOB pads can drive the four inputs to a lookup table for every slice in the FPGA. This routing overhead may impact the overall yield of known defective FPGA die which are able to be used with a given circuit. That is, the extensive routing to test a defective lookup table, and not the lookup table itself, may be the cause of the defect, and thus causing the device to be unnecessarily rejected.
Accordingly, there is a need for a method of efficiently testing circuits such as lookup tables of a programmable logic device.